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RM0008
6.3.1
Low-, medium- and high-density reset and clock control (RCC)
Clock control register (RCC_CR)
Address offset: 0x00
Reset value: 0x0000 XX83 where X is undefined.
Access: no wait state, word, half-word and byte access
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
PLL
RDY
r
PLLON
rw
Reserved
CSS
ON
rw
HSE
BYP
rw
HSE
RDY
r
HSE
ON
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
HSICAL[7:0]
HSITRIM[4:0]
Res.
HSI
RDY
HSION
r
r
r
r
r
r
r
r
rw
rw
rw
rw
rw
r
rw
Bits 31:26
Reserved, always read as 0.
Bit 25 PLLRDY: PLL clock ready flag
Set by hardware to indicate that the PLL is locked.
0: PLL unlocked
1: PLL locked
Bit 24 PLLON: PLL enable
Set and cleared by software to enable PLL.
Cleared by hardware when entering Stop or Standby mode. This bit can not be reset if the
PLL clock is used as system clock or is selected to become the system clock.
0: PLL OFF
1: PLL ON
Bits 23:20
Reserved, always read as 0.
Bit 19 CSSON: Clock security system enable
Set and cleared by software to enable clock detector.
0: Clock detector OFF
1: Clock detector ON if external 4-25 MHz oscillator is ready.
Bit 18 HSEBYP: External high-speed clock bypass
Set and cleared by software in debug for bypassing the oscillator with an external clock. This
bit can be written only if the external 4-25 MHz oscillator is disabled.
0: external 4-25 MHz oscillator not bypassed
1: external 4-25 MHz oscillator bypassed with external clock
Bit 17 HSERDY: External high-speed clock ready flag
Set by hardware to indicate that the external 4-25 MHz oscillator is stable. This bit needs 6
cycles of external 4-25 MHz oscillator clock to fall down after HSEON reset.
0: external 4-25 MHz oscillator not ready
1: external 4-25 MHz oscillator ready
Doc ID 13902 Rev 9
83/995
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